In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases (also known as a multi-phase clock). In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). When the voltage controlled delay loops are implemented using integrated circuit technology, an inherent mismatch exists between the various delay stages, causing uneven phase distribution of the multi-phase clock in the generated phases of the clock sources. It has been found that even a small processing mismatch can cause a large percentage mismatch in design output variability. A skew between the individual clock phases translates into eye closure and reduced jitter tolerance margins.
U.S. patent application Ser. No. 11/141,703, entitled, “Parallel Trimming Method and Apparatus for a Voltage Controlled Delay Loop,” discloses methods and apparatus for compensating for mismatched latch buffers associated with each delay element in the VCDL loop. The disclosed trimming process trims a plurality of delay units in a VCDL, where each delay unit comprises a delay element and a latch buffer. A reference signal, for example, from a central interpolator, is applied to each of the delay units and a position of an edge associated with each of the delay units, such as a rising or falling edge, is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
The same clock is applied as the reference signal to all the clock buffer paths, and an interpolator can be used to move the reference signal. While the disclosed trimming process effectively compensates for mismatched latch buffers, the disclosed techniques may change the delay of the latch buffer, because the reference signal for calibration will not have the same amplitude and slew rate as the signal used in steady-state data recovery. In addition, resistance-capacitance (RC) delays associated with the routing of the reference signal may affect the arrival of the clock edges at the clock buffers.
A need therefore exists for improved clock skew calibration techniques for a clock and data recovery system.